This invention relates to an image processor capable of displaying the images of video signals from a plurality of signal sources on the same screen at the same time.
There have been known display systems, such as monitoring systems, in which a plurality of video cameras are installed and moving pictures are reproduced from the video camera signals. An image memory is used, for example, for display so that the pictures are displayed simultaneously in small sections of the same screen. An example of this image processor is described in the publication "Television Technique", pp. 20-24, January 1987. The following explains the image processor in brief with reference to FIGS. 1 and 2. In the block diagram of FIG. 1 showing the basic arrangement of the image processor, indicated by 1 through 4 are input terminals of video signals, 5 through 8 are analog-to-digital (A/D) converters, 17 is a memory, 18 is a memory control circuit, 20 is a digital-to-analog (D/A) converter, and 21 is an output terminal.
The image processor has four video inputs, and these video signals A, B, C and D are received at the input terminals 1, 2, 3 and 4, respectively. The video signals A, B, C and D are converted into digital video signals by the respective A/D converters 5, 6, 7 and 8, and are stored in the memory 17 which is controlled by the memory control circuit 18.
In the memory 17, the digital video signals A, B, C and D are each written every other horizontal scanning line, with each intervening horizontal scanning line being removed, and stored in the specified areas. As shown in FIG. 2, the memory 17 has its column address and row address each split into two so that the whole 1-field area is divided into four areas, in which the digital video signals A, B, C and D are stored. Accordingly, an area A of the memory 17 stores the digital video signal A for one field, and in the same way areas B, C and D store the digital video signals B, C and D for one field, respectively.
The number of column addresses of each of the areas A, B, C and D in the memory 17 is made equal to the number of samples in one horizontal scanning period of the A/D converter 5, which has its sampling clock frequency made equal to the writing clock frequency of the memory 17.
The memory 17 is read at a reading clock frequency twice the writing clock frequency, and the whole storage address is read in the order of address in a period of field length. Assuming a number of column addresses of m and a number of row addresses of n, with the starting address being (0, 0) as shown in FIG. 2, the memory 17 is addressed for reading in the order of (0, 0), (1, 0), . . . , (m, 0), (0, 1), (0, 2), . . . , (0, n), (1, n), . . . ,(m, n). Reading of complete column addresses of one row takes a time of one horizontal scanning period.
The memory 17 stores the digital video signals A, B, C and D for one field in the specified areas, and at the same time its whole storage area is read out. Consequently, the digital video signals A, B, C and D read out of the memory 17 have each field compressed on the time axis.
The digital video signals read out of the memory 17 are converted into analog video signals by the D/A converter 20, and the signals are delivered to a monitor display (not shown) through the output terminal 21. On the monitor screen, the pictures carried by the video signals A, B, C and D are displayed in a 1/4 reduction size in four divided screen areas.
However, the foregoing prior art image processor has the following deficiencies.
The first problem is jitters caused by the clock. The memory 17 is addressed in time with the horizontal and vertical sync signals, and each address receives pixel data which is delayed by a certain time length from the horizontal sync signal of a horizontal scanning line at a certain position counted with respect to the vertical sync signal. In this case, if the A/D converters 5-6 have their sampling clock phase varied with respect to the horizontal sync signal, the sampling point of the video signals is shifted and incorrect pixels are sampled. Consequently, the memory 17 stores data which has been sampled at positions shifted from the specified positions based on the horizontal sync signal. In the conventional system, the sampling clock has its phase varied with respect to the horizontal sync signal as much as one sampling clock period. Reading out pixel data from the memory 17 to the monitor screen produces pictures in which all pixels are shifted in the horizontal direction, and since in the conventional system the A/D converters 5-8 have a relatively low sampling clock frequency, the horizontal displacement of displayed pictures is highly noticeable.
Especially, when the horizontal sync signals of the input video signals are out of phase with the sampling clock, each horizontal scanning line has a different shift in the horizontal direction, resulting in a display of notched vertical profiles and vertical lines. In order to prevent this defect, conventional systems have employed start oscillators controlled for stopping and starting in response to the horizontal sync signals or clock generators based on a PLL circuit or the like for producing clock signals as a multiple of the horizontal sync signals, thereby synchronizing the sampling clock signals of the A/D converters with the horizontal sync signals.
However, this technique necessitates individual clock generation circuits for all input video signals (A, B, C and D in FIG. 1), which unfavorably increases the circuit complexity and cost.
Another problem is the creation of a beat caused by the clock. Although the foregoing conventional image processor is operative for asynchronous input video signals A, B, C and D, this case results in asynchronous sampling clock signals for the A/D converters 5-8 and writing clock signals for the memory 17. These clock signals leak onto the video signal lines, although in a small degree, and the fluctuation of frequency or phase among the clocks creates a beat and eventually deteriorates the picture quality on the monitor screen.
This defect may be prevented by synchronizing all video signals so that a common clock is used. But such a modified system necessitates additional delay means and control means for the synchronization of video signals, resulting in an increased circuit complexity and cost.
An object of this invention is to solve the foregoing prior art deficiencies and provide an image processor capable of enhancing the picture quality without increasing the circuit complexity.
In order to achieve the above objective, the inventive image processor includes, for A/D conversion means of each video signal, a sync separation circuit which separates the sync signal from the video signal and a clock reduction circuit which is reset by the sync signal and adapted to reduce the clock frequency, with all clock reduction circuits of the A/D conversion means having an equal frequency reduction ratio and equal clock frequency, and the output signals of the clock reduction circuits being used as sampling clocks for A/D conversion.
Since the clock reduction circuit is reset by the sync signal, it produces a sampling clock with a phase difference, from the sync signal, of one input clock period of the clock reduction circuit at most, and it significantly reduces jitters as compared with the case of a sampling clock independent of the sync signal where the maximum phase difference is one sampling clock period. In addition, all A/D conversion means have an equal sampling clock frequency, and therefore beat is not created.